Circuit for generation of logic variables, using multiplexes and inverters

ABSTRACT

A circuit for the generation of combinatorial logic variables, having multiplexers and inverters, which has, for each input state defined by a combination of input variables, a uniquely defined output state defined by at least one output variable including first input variables of lower weighting; blocks of intermediate variables of the same size generated by the input variables of lower weighting, forming with logic combinations having switching behavior determined by further input variables of higher weightings.

This application is a continuation Ser. of application Ser. No. 781,826 filed Sept. 30, 1985 and now abandoned.

BACKGROUND OF THE INVENTION

The invention relates to a circuit for the generation of combinatorial logic with multiplexers and inverters, wherein each output state is uniquely defined by a combination of at least the input variable.

Circuits for combinatorial logic generation are part of the basic digital technology circuits that are realizable, according to the state of the art, with two-stage OR-AND or AND-OR gate arrangements, or by means of multiplexers and inverters. A basic requirement for the design of such circuits is the use of a minimum of switching elements within reasonable expenditure of time. As a rule, either minterms, i.e. conjunctions, or maxterms, i.e. disjunctions, of all variables are employed to solve the respective problem. Either those minterms which effect a high logic level in their desired function or those maxterms whose desired function has a low logic level are used.

Boolean algebra, the McCluskey method, or the Karnaugh diagrams, described in the book by K. Steinbuch and W. Rupprecht: "Nachrichten-Technik", 2nd edition, 1973, Springer-Verlag, Berlin, Heidelberg, New York, offer possibilities to minimize the circuit complexity. Multiplexer circuits, which in today's technologies have special hardware realizations, are usually minimized through computer algorithms such as described in the paper by A. B. Ektare and D. P. Mital "Simple Algorithm for Logic Design Using Multiplexers" in "The Radio and Electronic Engineer", Vol. 50 (1980), No. 7, pages 363 to 366.

The known circuit complexity minimization methods are either cumbersome, time consuming, or restricted to a certain number of input variables. The Boolean algebra employs purely formal methods without system, and the McCluskey method, while being schematic, is complicated; Karnaugh diagrams are easy to handle only up to five input variables, and determining the best control variables in multiplexer circuits requires either computer time or much time to find the solution by hand.

SUMMARY OF THE INVENTION

The invention has the object of solving the problem by means of a multiplexer circuit for combinatorial logic generation which works with a minimum of switching elements at a minimum expenditure of time for its design.

According to the invention, this problem is solved in a circuit of the kind described at the outset.

In one embodiment of the invention the generation of combinatorial logic with multiplexers and inverters is provided which has, for each input state defined by a combination of input variables, a uniquely defined output state defined by at least one output variable. The input variables (E_(i)) of the lowest binary weighting each (E₀, E₁ ; E₂, E₃) serve for the generation of blocks (A₁ ; A₁ ⁻) of the same size with logic combinations whose switching behavior is determined by the input variables of higher binary weightings (E₂, E₃ ; E₄, E₅).

In accordance with another feature of the invention, the circuit is based on dual binary logic.

In accordance with an added feature of the invention, the blocks are formed of combinations of 4 bits each.

In accordance with an additional feature of the invention, the bit combinations of the blocks (A_(i) ; A_(i) ') which are defined by the input variables of the respective lowest binary weighting (E₀, E₁ ; E₂, E₃) and a logic low and high level and that an input variable (E₁) applied to the address inputs (G) of multiplexers controls the switching behavior of the other input variables (E₀) applied to associated data inputs (0, 1) and/or of the low or high level.

In accordance with again another feature of the invention, the input variables of higher binary weighting (E₂, E₃ ; E₄, E₅) control address inputs of multiplexers (1, 2; 20 to 27).

In accordance with again an added feature of the invention, the blocks (A_(i) ; A_(i) ') from whose combinations the output states (S₁, S₂ ; B₂, B₁, B₀) associated with the possible input states can be formed are applied to the data inputs (0, 1, 2, 3; 0, 1) of the multiplexers (1, 2; 20 to 27) controlled by the input variables of higher weighting (E₂, E₃ ; E₄, E₅).

In accordance with again a further feature of the invention, the blocks with those 4 bit combinations whose combinations indicate the output states (S₁, S₂) for the input states defined by the input variables (E₀ to E₃) are applied to the data inputs (0, 1, 2, 3) of the multiplexers (1, 2) controlled by the input variables of the weightings 2² and 2³ (E₂, E₃).

In accordance with still another feature of the invention, the input variables of weightings greater than 2³ (E₀ to E₅) are involved, the input variables with weightings greater than 2¹ (E₂ to E₅) are decoded in stages in order to address the block (A_(i)) associated with four each consecutive input states and resulting in the output states.

In accordance with a concomitant feature of the invention, those blocks (A_(i)) generated by the input variables of the weightings 2⁰ and 2¹ (E₀, E₁) from whose combination the output states (S) of the circuit are formed are applied to the data inputs (0, 1, 2, 3) of the last multiplexer stage (10 to 12). In this way, there are applied to this stage coded output variables (B₂, B₁, B₀) of the next to the last multiplexer stage (20 to 27) which are defined by dual coding, in ascending order, of the blocks controlled by the binary weighting 2⁰ and 2¹ (E₀, E.sub.) and which control the multiplexers of the last stage (10 to 12) to address the block (A_(i)) which in turn determine the four, each consecutive, output stages of the circuit, and wherein the at most four binary weightings of the output variables (B_(i)) of the next to the last multiplexer stage (20 to 27) are again combined to blocks (A_(i) ') of 4 bits. These are applied to the data inputs (0, 1) of the next to the last multiplexer stage (20 to 27) and are now generated, corresponding to the blocks (A_(i)) generated by the input variables of the binary weightings 2⁰ and 2¹ (E₀, E₁), by the input variables of the binary weightings 2² and 2³ (E₂, E₃) and are switched through for the generation of coded output variables (B₂, B₁, B₀) with maximally four binary weightings, so that the address inputs (G) of the next to the last multiplexer stage (20 to 27) are controlled by again coded output variables of the next to the last multiplexer stage. The output variables are generated in accordance with the coding of the output variables (B₂, B₁, B₀) of the next to the last stage (20 to 27) and progress stepwise in this manner until the input variables of the binary weightings 2^(n-1) and 2^(n) (E₄, E₅ ) remain for the address inputs (G) of the multiplexers (20 to 27) of the last stage.

The embodiments of the inventive idea are defined in the claims.

The invention is explained below in greater detail with reference to three figures in which identical elements have the same reference symbols.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a circuit for logic generation with multiplexers, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:

FIG. 1 shows embodiment examples for the blocks of equal size with logic combinations, to be generated from input variables of respectively lowest weighting;

FIG. 2 shows an embodiment example of a circuit according to the invention with four input variables; and

FIG. 3 shows an embodiment example of a circuit according to the invention with six variables.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The idea underlying the invention is to generate, by means of the input variables of respectively lowest binary weighting, blocks of equal size forming logic combinations. The possible output states result from a combination of these blocks. The blocks occupy the data inputs of a multiplexer circuit and are switched through to the multiplexer circuit output in the combinations of the input variables to which the logic combinations of the blocks are assigned. The selection of the respectively correct block is determined by the input variables of higher binary weighting which occupy the address inputs of the multiplexer circuit.

Besides the little time consumed in minimizing the switching elements required, the easy changeability of the desired function which indicates the output states determined by the input states represents another advantage of the circuit according to the invention. When needed, all that is necessary is to exchange the blocks applied to the data inputs of the multiplexer circuits. Further advantages of the circuit according to the invention are seen in that up to eight input variables can be handled very easily without computer and in that the switching time becomes independent of the function of the output variables. Advantageous fields of application for such multiplexer circuits are gate arrays, especially in ECL technology.

For use in dual binary logic, standard multiplexers are available which have either one address input and two data inputs or two address inputs and four data inputs, with one output each. The logic state of a control variable applied to the address inputs determines which ones of the variables applied to the data inputs are to be switched through to the output. For example, the address variables 00, 01, 10, 11 control, in this sequence, the data inputs 0, 1, 2, 3 associated with them. The fan-out is up to 10, but at higher output loads buffer amplifers are required. Due to the special hardware realization used for the multiplexers, the output variables are usually available inverted also; otherwise, inverters are required, as for the input variables.

Now, according to the invention, the input variables of respectively lowest binary weighting serve for the generation of blocks of 4-bit size with 16 different combinations resulting from the variation of the bits.

While the generation of the larger blocks, e.g. of 8 bits, is also possible, it becomes impractical to handle the 256 combinations then resulting. The combinations of the 4-bit blocks of intermediate variables A₀ to A₁₅ listed below can be generated by means of the two input variables of lowest binary weighting E₀ and E₁.

                                      TABLE 1                                      __________________________________________________________________________     E.sub.1                                                                          E.sub.0                                                                          A.sub.0                                                                          A.sub.1                                                                          A.sub.2                                                                          A.sub.3                                                                          A.sub.4                                                                          A.sub.5                                                                          A.sub.6                                                                          A.sub.7                                                                          A.sub.8                                                                          A.sub.9                                                                          A.sub.10                                                                          A.sub.11                                                                          A.sub.12                                                                          A.sub.13                                                                          A.sub.14                                                                          A.sub.15                                __________________________________________________________________________     0 0 0 1 0 1 0 1 0 1 0 1 0  1  0  1  0  1                                       0 1 0 0 1 1 0 0 1 1 0 0 1  1  0  0  1  1                                       1 0 0 0 0 0 1 1 1 1 0 0 0  0  1  1  1  1                                       1 1 0 0 0 0 0 0 0 0 1 1 1  1  1  1  1  1                                       __________________________________________________________________________

The index i designating the blocks A_(i) of intermediate variables corresponds in the decimal number system to the bit combination of the associated block in the binary number code. The blocks A₁₅ to A₈ follow in this sequence from the inversion of the blocks A₀ to A₇. The block A₀ represents the logic low level, and the blocks A₃ and A₅ are the inversions of the input variables E₁ and E₀. The logic low or high level and the input variables E₀ and E₁ need not be generated separately because they must necessarily be available for a circuit according to the invention. Assuming that each bit sequence is available also in inverted form or was generated by inversion, there remain five blocks which must be generated by means of multiplexers.

FIG. 1 represents the five associated circuits in the part figures a to e under the assumption that the input variable E₁ is the control variable. There then remain for the data inputs 0 and 1 the logic low or high level and the input variable E₀. FIG. 1a corresponds to block A₁ : At the logic low level of the address input G or the input variable E₁ the inverted input variable becomes E₀ ; at the logic high level of the address input G the logic low level is connected to the output. Correspondingly, the circuit per FIG. 1b generates the block A₂, per FIG. 1c the block A₄, per FIG. 1d the block A₆, and per FIG. 1e the block A₇.

The blocks can be generated just as readily when instead of the input variable E₁ the input variable e₀ occupies the address input G. In that case, Block A₁ can be generated by the inverted input variable E₁ at the data input 0 and the logical low level at the data input 1 of a multiplexer. Thus, the realization of all 16 output combinations of the blocks A₀ to A₁₅ is possible by means of 5 multiplexers, each with two data inputs and one output, and the inversion of the outputs. It is assumed for the further description that the blocks A₀ to A₁₅ are generated and are available for data inputs.

In the first embodiment example of a circuit according to the invention, the input stages defined by the possible combinations of four input variables E₀ to E₃ are to lead to two output states, each represented by one output variable. The output states are specified by the desired functions S₁ and S₂. The problem may also be interpreted as the generation of one output state with two output variables each. The binary weighting of the input variables is as indicated by their index, the input variable E₀, for instance, having the binary weighting 2⁰, the input variable E₁ the binary weighting 2¹, etc.. The output states associated with the combinations of the input variables are listed below.

                  TABLE 2                                                          ______________________________________                                         E.sub.3                                                                              E.sub.2   E.sub.1                                                                              E.sub.0 S.sub.1  S.sub.2                                 ______________________________________                                         0     0         0     0       1        0                                       0     0         0     0       0        1                                                                         A.sub.13                                                                                A.sub.10                            0     0         1     0       1        0                                       0     0         1     1       1        1                                       0     1         0     0       0        0                                       0     1         0     1       0        1                                                                         A.sub.4                                                                                 A.sub.6                             0     1         1     0       1        1                                       0     1         1     1       0        0                                       1     0         0     0       0        1                                       1     0         0     1       1        0                                                                         A.sub.2                                                                                 A.sub.1                             1     0         1     0       0        0                                       1     0         1     1       0        0                                       1     1         0     0       1        0                                       1     1         0     1       0        1                                                                         A.sub.5                                                                                 A.sub.14                            1     1         1     0       1        1                                       1     1         1     1       0        1                                       ______________________________________                                    

According to the invention, the successive output states of the output variables are divided into 4-bit blocks. Thus, the output state of the desired function S₁ associated with the decimal input states 0 to 3 corresponds to the block A₁₃ and the output state of the desired function S₂ to the block A₁₀. As the above table indicates, the output states associated with the rest of the input states are handled correspondingly.

The input variables E₀ and E₁ were already used to generate the blocks A₀ to A₁₅. There remain the input variables E₂ E₃ which occupy the address inputs of a multiplexer with four data inputs. Applied to the multiplexer data inputs are those blocks A_(i) listed in the above table which result in the desired functions S₁ and S₂ if appropriately controlled by the input variables E₂ and E₃. Two multiplexers, each with four data inputs and one output, are required for the two desired functions, each defined by four blocks. FIG. 2 shows the circuit according to the invention pertaining thereto.

In each one of the four possible states of the address inputs A0 and A1 a complete block applied to the multiplexer 1 and 2 data inputs 0 to 3 associated with them must be connected to the output. Although no special decoder is required, decoding of the input variables E₂ and E₃ occurs solely in that they drive the address inputs A0 and A1 of the binary weightings 2⁰ and 2¹. Therefore, in the 00 state of the input variables E₂ and E₃, the data inputs 0 of the multiplexers 1 and 2 assigned to them, with the blocks A₁₃ and A₁₀, can be switched through to the output. Triggering the data inputs 0 to 3 of the multiplexers 1 and 2, occurring in ascending order of the address inputs A0 and A1 or of the input variables E₂ and E₃, then results in the desired function S₁ in the multiplexer 1 and S₂ in the multiplexer 2.

Compared with realizations of these desired functions S₁ and S₂ possible by the prior art using minterms and maxterms, the circuit according to the invention as shown in FIG. 2 requires fewer or at the most as many components and less or at the most as much space. The desired function is modified simply by rerouting the blocks applied to the data inputs of the multiplexers.

The advantages of a circuit according to the invention usually bear fruit only when there are more than four input variables, as is demonstrated for the second embodiment example with 6 input variables. A special decoder to drive the multiplexers is required in the second embodiment example. In this case, the desired function S to be generated and defined by one output variable is again divided into blocks of 4 bits each for the input and output states in the following coordination table.

Corresponding to the 2⁶ -64 input states and, hence, 64 output states are 16 blocks of 4 bits each. In the case of the example, of the 16 possible blocks defined by the input variables E₀ and E₁, there are seven different blocks. The switching behavior of these blocks is determined by the input variables E₂ to E₅. Since a maximum of two input variables can address a multiplexer, a decoder is required in the case of the example.

                                      TABLE 3                                      __________________________________________________________________________     E.sub.5                                                                          E.sub.4                                                                          E.sub.3                                                                           E.sub.2                                                                          E.sub.1                                                                           E.sub.0                                                                          S    E.sub.5                                                                          E.sub.4                                                                          E.sub.3                                                                           E.sub.2                                                                          E.sub.1                                                                           E.sub.0                                                                          S                                             __________________________________________________________________________     0 0 0  0 0  0 0    1 0 0  0 0  0 0                                             0 0 0  0 0  1 1    1 0 0  0 0  1 1                                                               A.sub.2            A.sub.10                                  0 0 0  0 1  0 0    1 0 0  0 1  0 0                                             0 0 0  0 1  1 0    1 0 0  0 1  1 1                                             0 0 0  1 0  0 0    1 0 0  1 0  0 1                                             0 0 0  1 0  1 1    1 0 0  1 0  1 1                                                               A.sub.2            A.sub.7                                   0 0 0  1 1  0 0    1 0 0  1 1  0 1                                             0 0 0  1 1  1 0    1 0 0  1 1  1 0                                             0 0 1  0 0  0 1    1 0 1  0 0  0 1                                             0 0 1  0 0  1 1    1 0 1  0 0  1 0                                                               A.sub.7            A.sub.13                                  0 0 1  0 1  0 1    1 0 1  0 1  0 1                                             0 0 1  0 1  1 0    1 0 1  0 1  1 1                                             0 0 1  1 0  0 0    1 0 1  1 0  0 0                                             0 0 1  1 0  1 0    1 0 1  1 0  1 1                                                               A.sub.8            A.sub.2                                   0 0 1  1 1  0 0    1 0 1  1 1  0 0                                             0 0 1  1 1  1 1    1 0 1  1 1  1 0                                             0 1 0  0 0  0 0    1 1 0  0 0  0 0                                             0 1 0  0 0  1 1    1 1 0  0 0  1 0                                                               A.sub.6            A.sub.8                                   0 1 0  0 1  0 1    1 1 0  0 1  0 0                                             0 1 0  0 1  1 0    1 1 0  0 1  1 1                                             0 1 0  1 0  0 0    1 1 0  1 0  0 1                                             0 1 0  1 0  1 1    1 1 0  1 0  1 1                                                               A.sub.10           A.sub.11                                  0 1 0  1 1  0 0    1 1 0  1 1  0 0                                             0 1 0  1 1  1 1    1 1 0  1 1  1 1                                             0 1 1  0 0  0 1    1 1 1  0 0  0 0                                             0 1 1  0 0  1 1    1 1 1  0 0  1 1                                                               A.sub.11           A.sub.6                                   0 1 1  0 1  0 0    1 1 1  0 1  0 1                                             0 1 1  0 1  1 1    1 1 1  0 1  1 0                                             0 1 1  1 0  0 1    1 1 1  1 0  0 0                                             0 1 1  1 0  1 0    1 1 1  1 0  1 1                                                               A.sub.13           A.sub.2                                   0 1 1  1 1  0 1    1 1 1  1 1  0 0                                             0 1 1  1 1  1 1    1 1 1  1 1  1 0                                             __________________________________________________________________________

For the design of the decoder, the distinguishable, i.e. uniquely identifiable, blocks are binary coded in ascending order.

                  TABLE 4                                                          ______________________________________                                         Block      B.sub.2       B.sub.1                                                                              B.sub.0                                         ______________________________________                                         A.sub.2    0             0     0                                               A.sub.7    0             0     1                                               A.sub.8    0             1     0                                               A.sub.6    0             1     1                                               .sup. A.sub.10                                                                            1             0     0                                               .sup. A.sub.11                                                                            1             0     1                                               .sup. A.sub.13                                                                            1             1     0                                               ______________________________________                                    

Assigned to the distinguishable blocks A_(i) are the code variables B₀ to B₂ of the weightings 2⁰ to 2². Each code word defined by the code variables B₀ to B₂ stands for four output states defined by the input variables E₀ and E₁. A maximum of 4 code variables B_(i) is required for the greatest number of 16 distinguishable blocks A_(i) which can occur. Consequently, the decoder can handle 4 input variables and be built as a single stage unit, analogous to the case treated in the first embodiment example. At more than six input variables, those having weightings greater than 2¹ are decoded in several stages. By means of the decoded variables, the last multiplexer stage connects the blocks, generated by E_(o) and E, to the output.

In the present embodiment example, the output states defined by the coded output variables =code variables B₀ to B₂ are associated with the input variables E₂ to E₅. Each code variable B_(i) can be considered as a desired function to be realized. Corresponding to the first embodiment example, the input variables E₂ and E₃ assume for the decoder the task of generating blocks of 4 bits each. These blocks are applied to the data inputs of the decoder multiplexers addressed by the input variables E₄ and E₅. In the embodiment example, the decoder has 3 outputs, each associated with one code variable B_(i) and driving the succeeding multiplexers to whose data inputs are applied to the blocks generated by the input variables E₀ and E₁. The result is the following relationship, which also contains the actual desired function S to be generated, in the form of the blocks generated by the input variables E₀ and E₁.

                  TABLE 5                                                          ______________________________________                                         E.sub.5                                                                            E.sub.4                                                                              E.sub.3                                                                               E.sub.2                                                                            B.sub.2                                                                            B.sub.1                                                                             B.sub.0                                                                            B.sub.2                                                                             B.sub.1                                                                             B.sub.0                                                                             S (E.sub.1,                   ______________________________________                                                                                          E.sub.0)                      0   0     0      0   0   0    0   A.sub.0 '                                                                           A.sub.8 '                                                                           A.sub.4 '                                                                           A.sub.2                       0   0     0      1   0   0    0                  A.sub.2                       0   0     1      0   0   0    1                  A.sub.7                       0   0     1      1   0   1    0                  A.sub.8                       0   1     0      0   0   1    1   .sup. A.sub.14 '                                                                    A.sub.9 '                                                                           A.sub.5 '                                                                           A.sub.6                       0   1     0      1   1   0    0                  .sup. A.sub.10                0   1     1      0   1   0    1                  .sup. A.sub.11                0   1     1      1   1   1    0                  .sup. A.sub.13                0   1     0      0   0   1    0   A.sub.5 '                                                                           A.sub.4 '                                                                           A.sub.2 '                                                                           .sup.  A.sub.10               1   0     0      1   0   0    1                  A.sub.7                       1   0     1      0   1   1    0                  .sup. A.sub.13                1   0     1      1   0   0    0                  A.sub.2                       1   1     0      0   0   1    0   A.sub.2 '                                                                           A.sub.5 '                                                                           A.sub.6 '                                                                           A.sub.8                       1   1     0      1   1   0    1                  .sup. A.sub.11                1   1     1      0   0   1    1                  A.sub.6                       1   1     1      1   0   0    0                  A.sub.2                       ______________________________________                                    

In this case, the code variable or coded output variable B₂ of the decoder can be presented by the blocks A₀ ', A₁₄ ', A₅ ' and A₂ '. The ' is to indicate that these blocks, although having the same bit sequence as the blocks generated by the input variables E₀ and E₁, are generated in this case by the input variables E₂ and E₃. The two input variables E₄ and E₅ can now be used as address inputs for multiplexers because there is only a maximum of 16 different blocks A_(i) '. In this case, 12 blocks are used.

Now, the decoder belonging to the second embodiment example may be designed like the circuit according to the invention of the first embodiment example.

But in the circuit according to the invention as shown in FIG. 3 another avenue is chosen, resulting directly from the coordination table for the blocks A_(i) '. Therein, the input variable E₄ controls the address inputs of five multiplexers 20 to 24 with two data inputs 0 and 1 each. Since the blocks A₄ ' and A₅ ' are coordinated twice equally with the states of the input variables E₄ only five multiplexers driven by E₄ are sufficient.

Starting at the highest weighting of the code variables B_(i), the blocks A_(i) ' are applied in ascending order relative to the input variables E₄ and E₅ to the data inputs 0 and 1 of the multiplexers 20 to 24. Since two blocks each are associated with each logic state of the input variables E₅, the outputs of the multiplexers controlled by E₄ represent at the same time the data inputs 0 and 1 of the succeeding multiplexers 25 to 27 controlled by E₅. The exception are the blocks A₄ ' and A₅ ' controlled by E₄ and coordinated, on the one hand, with the low level of E₅ for the generation of the code variables B₀ and, on the other hand, with the high level of E₅ for the generation of the code variables B₁. The code variables B₀, B₁ and B₂ are then available at the decoder output.

For the seven distinguishable blocks A_(i) coordinated with the input variables E₀ to E₅ two multiplexers 10 and 11 with four data inputs 0 to 3 each are needed in the last multiplexer stage of the circuit. The address inputs A0 and A1 for these multiplexers occupy the lowest weighting code variables, namely B₀ and B₁. The choice between the blocks switched through by these code variables to the output of the multiplexers 10 and 11 is made by a multiplexer 12 of the last multiplexer stage with two data inputs 0 and 1 controlled by the code variable B₂. The desired function S for the 6 input variables E₀ to E₅ is then available at the output of this multiplexer.

A circuit with more than eight blocks controlled by the input variables E₀ and E₁ looks similar thereto because four code variables B_(i) of different weightings will then serve as address inputs. For more than 6 input variables E_(i) the decoder design is repeated stepwise until the input variables of the weighting 2^(n-1) and 2^(n) remain as address inputs for multiplexers.

The foregoing is a description corresponding in substance to German Application P 34 35 774.2, dated Sept. 28, 1984, the International priority of which is being claimed for the instant application, and which is hereby made part of this application. Any material discrepancies between the foregoing specification and the aforementioned corresponding German application are to be resolved in favor of the latter. 

I claim:
 1. Circuit for the generation of combinatorial logic variables, formed of multiplexers having multiple data and address inputs and multiple binary input and output states and inverters , said circuit having for each input state defined by a combination of input variables of lowest binary weight, a uniquely defined output state defining at least one output variable, said circuit comprising first means for receiving a plurality of first input variables of lowest binary weight; second means connected to said first means for generating intermediate variables of equal binary weightbeing a logic function of the input variables of lowest binary weight, and third means connected to said second means including logic combinations having further input variables of higher binary weights to generate said at least one output variable.
 2. Circuit according to claim 1, wherein said intermediate variables have binary weights equal to four
 3. Circuit according to claim 1,wherein the intermediate variables are further defined by the input variables of the lowest binary weight and by at least one further input variable of higher binary weight, logic low and high level multiplexers having address inputs controlled by the further input variable, and data means for receiving said first input variables of the lower binary weight.
 4. Circuit according to claim 1 wherein said third means include multiplexers having address inputs for receiving said input variables of higher binaryweight.
 5. Circuit according to claim 4, wherein the intermediate variables are each defined as a combination of the input states, and are applied to the data inputs of the multiplexers controlled by the input variables of higher binaryweights.
 6. Circuit according to claim 5including further intermediate variables each having four bit combinations, said each further intermediate variables having at least two output states, defined by said first variables, said further intermediate variables being applied to the data inputs of the multiplexers controlled by said further input variables having lowest binary weights
 7. Circuit according to claim 5, including input variables having binary weights greater than 2³, the input variables having binary weights greater than 2¹ being decoded in stages for addressing the intermediate variables.
 8. Circuit according to claim 7, including a last and a next to last multiplexer stage, wherein at data inputs of the last multiplexer stage the blocks generated by the input variables having weights adjacent to the weights 2⁰ and 2¹ form further intermediate variables, and wherein at the address inputs adjacent to the last multiplexer stage coded output variables of the next to last multiplexer stage ar defined by the input variables having weights 2⁰ and 2¹, wherein the multiplexer of the last stage control four consecutive output variables for the selection of the respective determining block, wherein no more than four weights of the output variables of the next to last multiplexer stage respectively are being combined, which are adjacent to the data inputs of the next to last multiplexer stage, and wherein respective blocks of the input variables with the weights 2⁰ and 2¹ (E₀, E₁) are generated by the input variables of the weights 2₂ and 2³, said input variables of weights 2² and 2³ being connected through for generation of coded output variables having a maximum of four weights, wherein the address inputs of the next to last multiplexer stage are again controlled by coded output variables of th second to last multiplexer stage, said coded variables are generated corresponding to the coding of the output variables of the next to last stage, and stage-by-stage progressing in such a way, until only the input variables of the weights 2^(n-1) and 2^(n) for multiplexer address inputs remain. 